1. Field of the Invention
The invention relates in general to a receiver system, and more particularly to a receiver system for automatic skew-tuning.
2. Description of the Related Art
FIG. 1A shows a block diagram of a conventional receiver system 100. The receiver system 100 is for sampling N bit data Di according to an input clock signals Ci during the period Tc, so as to output N output data Dt. Each of the N output data Dt is sampled from one of the N bit data Di. The N bit data Di includes bit data Di(1) to Di(N). The delay-locked loop (DLL) unit 110 generates N clock signals Ck based on the input clock signal Ci. The N clock signals Ck include clock signals Ck(1) to Ck(N). The period of each of the N clock signals Ck is equal to the period of the input clock signal Ci. The clock signal Ck(i+1) lags behind its previous clock signal Ck(i) by 1/N of the period of the input clock signal Ci. The number i is a positive integer smaller than N. The data latch unit 120 samples the serial bit data Di(1) to Di(N) respectively with the clock signals Ck(1) to Ck(N), so as to output the N output data Dt, which includes output data Dt(1) to Dt(N), in parallel.
FIG. 1B is an example of a timing diagram of the N bit data Di and the clock signals Ck(1) to Ck(N) in the period Tc. Referring to FIG. 1B, in this example, the N bit data Di are sampled on the rising edge of the N clock signals Ck. In this example, each bit data is transmitted during one bit time, which is equal to 1/N of the period Tc of the initial clock signal Ci. The skew between the bit data Di(i) and the clock signal Ck(i) is define as the time interval between the middle point of the bit time of the bit data Di(i) and the rising edge of the clock signal Ck(i).
Take the bit data Di(1) as example. In FIG. 1B, the bit data Di(1) is transmitted during the bit time Tb(1). The skew between the bit data Di(1) and the clock signal Ck(1) is the time interval between the middle point of the bit time Tb(1) and the rising edge of the clock signal Ck(1). In the example shown in FIG. 1B, the skew between the bit data Di(1) and the clock signal Ck(1) is small, therefore the bit data Di(1) is correctly sampled on the positive edge of the clock signal Ck(1) during the middle region M(1) of the bit data Di(1).
However, the skews between each of the N bit data Di and its corresponding clock signals Ck may be too large which causes that the N bit data Di can not be sampled correctly. FIG. 1 C is another example of a timing diagram of the N bit data Di and the clock signals Ck(1) and Ck(N). Referring to FIG. 1 C, take the sampling procedure of the bit data Di(1) as an example. The skew SK between the bit data Di(1) and the clock signal Ck(1) is about half of the bit time Tb(1), and the bit data Di(1) is sampled during the data transition area T1. As a result, an incorrect output data Dt(1) is obtained. Therefore, if the skew between each bit data and its corresponding clock signal is too large or if the bit time of each bit data Di is too short, the data latch unit 140 may sample the bit data during the transition area between each bit data Di. Then, the incorrect output data Dt is obtained. Consequently, how to design a receiver system capable of overcoming the skew problem is highly desired.